1. Field of the Invention
The present invention relates to the field of information technology, and more specifically, to a multi-bit error correction method and apparatus based on a BCH code and a memory system.
2. Description of the Related Art
With the advent and improvements to semiconductor technology, the ability to manufacture several hundred million transistors on a single chip has been realized. With each improvement, such transistors are increasingly miniaturized, as additional transistors are placed in the same space. This miniaturization, however, poses challenges to the reliability of such devices and systems.
In the design of semiconductor memory systems, redundancy bits are widely introduced to ensure a high level of reliability. Generally, in memory systems, redundancy bits are added by encoding data in a certain manner when the data are stored. On the other hand, when the data are read, the data are decoded in a corresponding manner, and in the decoding process, the redundancy bits are utilized to perform error correction.
Traditionally, single-bit error correction has always been the main technology in memory systems. In such a technology, error correction processing can only correct one bit of the processed data at one time. However, with the continuous miniaturization and the continuous increase of the storage capacity of memory systems, the frequency of occurrences of bit errors increases.
For example, for the NAND flash memory that can store a large amount of data at a relatively low silicon cost, Multi-Level Cell (MLC) technology can double the bit storage capacity per cell in the NAND Flash memory, while reducing the total die size. However, as compared with the standard Binary-Level Cell (BLC) technology, the reliability of the NAND flash memory that adopts the MLC technology is comparatively lower, and its performance is much lower than that of the NAND flash memory that adopts the BLC technology.
FIG. 1 shows the reported comparison of error probability between the BLC-flash memory and the MLC-flash memory. The stated EDC/ECC capability denotes the error detection/correction capability, and NA denotes that the report data is not available for the current condition. As shown in FIG. 1, as compared with the BLC-flash memory, the MLC-flash memory exhibits an increase in the error probability, namely the frequency of occurrences of errors.
In order to cope with the increase of the error frequency, an effective multi-bit error correction method is needed to improve the efficiency of error correction. The so-called multi-bit error correction allows error correction processing to correct multiple bits of the processed data at one time. At present, there are technologies that adopt Bose/Ray-Chaudhuri (BCH) codes to implement multi-bit error correction. That is, data are encoded and decoded by using BCH codes, and in the decoding process, the redundancy bits added in the BCH encoding process are utilized to perform error correction. BCH codes have a considerably high capability of error correction and a capability of correcting multiple errors. Developers can construct the generation polynomial of BCH codes according to the required error correction capability, and further, utilize the constructed generation polynomial to construct the corresponding BCH codes.
However, the existing multi-bit error correction technologies that adopt BCH codes are all implemented based on short BCH codes. That is, the error correction capabilities implemented by these technologies are only limited to relatively short BCH codes generated by utilizing simple generation polynomials. As compared with relatively long BCH codes, the error correction manner based on relatively short BCH codes has a relatively low code density (the proportion of the number of bits occupied by valid data bits to the number of the bits of the whole BCH code), because the proportion of the redundancy bits introduced in the case of the error correction manner based on relatively short BCH codes is necessarily greater than that in the case of the error correction manner based on relatively long BCH codes.
Consider the following example. In the case of 32-bit relatively short BCH codes, it is assumed that each 32-bit BCH code contains 8 bits of redundancy introduced thereinto; however, if long BCH codes such as 1000-bit BCH codes are adopted, it is possible to cause each 1000-bit BCH code to contain 8 bits of redundancy introduced thereinto as well. Accordingly, in the case where long BCH codes are adopted, the proportion taken up by valid data bits will increase remarkably and a relatively high code density can be obtained, whereby the effective utilization of memory space can be achieved.
However, since as compared with relatively short BCH codes, the complexity of decoding of relatively long BCH codes increases sharply, at present, there exist no technologies that implement multi-bit error correction based on relatively long BCH codes.